Computer systems using single or multiprocessor architectures often include on a chip a set of counters allowing for counting processor events and system events. Statistic counters or performance measurement or monitor counters are used for counting for example floating point operations or cache misses, just to name a few countable events indicative of system performance. Event statistics for example help monitor an application and analyze its performance. Statistics may be easily acquired in hardware and may provide a feedback mechanism for application tuning, even on highly parallel systems.
Distributed network systems for example interconnecting computers, contain communication processors dedicated for example to packet classification and modification, packet forwarding or queuing policy management. Events indicative for system performance are for example packet retransmission rates, queue overflow etc.
For high-performance systems, many event counters are required and are often implemented, at the cost of high power consumption and increased die area and production cost, using fast data flip-flops (DFF) receiving the clock signal, allowing all counters to count at full clock-speed, probably in parallel, while low-performance systems may contain inexpensive random access memory (RAM) devices for storing counter values. Performance measurement counters typically count at full clock rate, and are therefore usually implemented as purely DFF based counters.
In US 2008/0043899 A1, a hybrid counters array is presented, wherein an array of counters is dedicated to hold the least significant (LS) bits (or binary digits) of binary representations of performance counter values while RAMs such as dynamic RAMs (DRAMs) are dedicated to hold the most significant (MS) bits. The used RAM may require initialization. In the shown system, counters are re-set in a reset sequence. Counters can start counting together after completion of the sequence. The shown system increments LS-bits counters and calculates roll-over bits for triggering incrementation of MS bits stored in the RAM.
In U.S. Pat. No. 7,293,158 B2, a system for implementing counters in a network processor is shown. The system uses an inexpensive, slow dynamic RAM (DRAM) coupled to a register pipeline capable of handling one event at a time. A counter controller may increment counter values more than once during a read-modify-write cycle initiated for the counter.